1. Field
The present disclosure pertains to the field of information processing, and, more specifically, to the field of transactions between input/output devices and memory in information processing systems.
2. Description of Related Art
Direct cache access “DCA” is an information processing system protocol that permits data from an input/output (“I/O”) device to be placed into a processor's cache. DCA may be used to avoid system memory access latency and bandwidth restrictions by placing the data into the processor's cache before, instead of, or in parallel with placing the data into system memory, or by placing the data into system memory or an intermediate cache and using a prefetch hint to trigger the placement of the data into the processor's cache.
The DCA protocol involves the use of DCA attributes, assigned per I/O transaction, that may determine whether DCA is enabled or disabled for a particular transaction, which processor's cache the data is to be placed into, how the data is to be placed into the processor's cache (e.g., in which way of a multi-way cache, and in what line state, e.g. exclusive or modified), or other details of a DCA transaction. Some of these attributes may be implementation or platform specific, for example, in a prefetching approach, the DCA attributes may include a length attribute for multi-line prefetches or a prefetch stride.
The DCA attributes are typically passed, in a peripheral bus transaction, from an I/O device to a chipset that encodes a corresponding transaction on a processor bus to pass the data to the processor's cache. For example, FIG. 1 illustrates a known approach to performing a DCA transaction in system 100, in which processors 110 and 120 are coupled to chipset 130 through processor bus 105. Chipset 130 is coupled to I/O device 140 through peripheral bus 135. Processor 110 includes core 112 and cache 113, core 114 and cache 115, core 116 and cache 117, and core 118 and cache 119. Processor 120 includes core 122 and cache 123, core 124 and cache 125, core 126 and cache 127, and core 128 and cache 129.
A DCA transaction in system 100 includes I/O transaction 150 on peripheral bus 135, where I/O transaction 150 includes field 151 to specify an address and/or data and field 152 to specify DCA attributes for the transaction. Chipset 130 receives I/O transaction 150, decodes the contents of fields 151 and 152, if necessary, and encodes system transaction 160. System transaction 160 includes field 161 to specify an address and/or data and field 162 to specify DCA attributes for the transaction. In FIG. 1, system transaction 160 is performed on processor bus 105 and targets cache 115.
The use of different peripheral busses, such as Peripheral Component Interconnect (“PCI”), PCI-X, PCI-Express, and Universal Serial Bus (“USB”), in different information processing systems may require varied approaches to passing DCA attributes in an I/O transaction. For example, since DCA did not exist when PCI-Express was defined, there are no PCI-Express fields that may be allocated exclusively for DCA use. Therefore, a custom approach to a DCA transaction on a PCI-Express bus may, for example, use a limited five-bit portion of the “tag” field in a PCI-Express transaction.
The use of such varied approaches, rather than a standard approach across different I/O buses, may limit the broad adoption of DCA.